The present invention relates generally to integrated circuits, and, more particularly, to an integrated circuit for configuring an external dynamic random access memory (DRAM).
Many integrated circuits (ICs) today include multiple components such as a processor and peripherals that are controlled by the processor. The peripherals include components such as memory controllers and a data bus. Such ICs are designed for specific applications such as those in automobiles and wireless communication devices. Based on the application, a processor of an IC executes a boot program that enables the IC to perform various functions that are programmed in an operating system (OS). The IC also includes an internal memory, such as a static random-access memory (SRAM) and a flash memory. The internal memory has a lower access time than external memories, such as dynamic random-access memory (DRAM) and programmable read-only memory (PROM). Hence, the internal memory is used to store data that is frequently accessed by the processor. Such data are also referred to as cache data. The external memories, which are external to the IC, have a larger capacity for storing data than the internal memories.
Internal memories are more expensive than external memories. Hence, to reduce the cost of the IC, the size of the internal memory is usually quite small. The OS is generally very large in size and exceeds the size of the internal memory. Hence, the OS is stored in an external memory.
A PROM is a non-volatile memory whereas a DRAM is a volatile memory. Thus, the PROMs are capable of persistent storage of data as compared to the DRAMs, and hence, the PROMs are suitable for storing the OS. However, the PROMs have a higher access time than the DRAMs and hence, the PROMs are unsuitable as a memory source for the processor to execute the OS from. To enable faster execution, all or part of the OS is copied from the PROM and stored in the DRAM.
The memory controller (i.e. a DRAM controller) enables the processor to access the DRAM. The DRAM controller receives instructions from the processor and sends commands to the DRAM by way of input/output (IO) pads to read and write data to/from the DRAM. However, since the DRAM is a volatile memory, the DRAM retains stored data for a short period of time. Thus, the DRAM must be constantly refreshed to enable persistent data storage. The DRAM operates in a refresh mode and a self-refresh mode. When the DRAM is in the refresh mode, the DRAM controller sends commands to the DRAM to refresh the DRAM at periodic time intervals. When the DRAM is in the self-refresh mode, the DRAM is capable of refreshing independent of the DRAM controller. To configure the DRAM in self-refresh mode, Joint Electron Device Engineering Council (JEDEC) standards require a DRAM RESET pin be at a logic high state and a clock enable (MCKE) pin of the DRAM to be at a logic low state. Generally, a RESET IO pad is used as an interface between the DRAM controller and the DRAM RESET pin and a MCKE IO pad is used as an interface between the DRAM controller and the DRAM MCKE pin. Thus, according to the JEDEC standards, when the DRAM is in self-refresh mode, the RESET and MCKE IO pads need to be kept high and low, respectively.
To reduce power consumption of the IC, the IC is operable in high and low power modes. When the IC is in the high power mode, the processor and the peripherals of the IC are operational. When the IC transitions from the high power mode to the low power mode, a state machine of the IC configures the processor and the peripherals in a sleep mode. In the sleep mode, the processor and the peripherals are either power-gated or clock-gated. When the IC transitions from low power mode to high power mode, the processor is powered on and starts executing OS instructions based on a boot vector stored in the internal memory. The boot vector is indicative of a stored state of the OS at which the IC transitions from the high to low power mode and enables the IC to resume operation from the stored state when the IC goes from the low power mode to the high power mode.
When the IC is in the high power mode, the DRAM controller refreshes the DRAM and enables persistent storage of the OS in the DRAM. When the IC transitions from the high power mode to the low power mode, it is desirable to power-gate the DRAM controller and the RESET and MCKE IO pads to reduce power consumption of the IC in the low power mode. Further, to reduce the transition time required for the IC to transition from the low power mode to the high power mode, it is desirable to keep the OS in the DRAM to save the time required to copy the OS from the PROM to the DRAM. Hence, it is desirable to configure the DRAM in the self-refresh mode to enable retention of the OS in the DRAM when the IC is in the low power mode. However, the DRAM controller is required to maintain the logic states of the RESET and MCKE pins of the DRAM. Thus, the DRAM controller and the RESET and MCKE IO pads need to be powered when the IC is in the low power mode, which increases power consumption.
A known technique to overcome this problem is to tie the DRAM MCKE pin to a termination voltage and connect the DRAM RESET pin to a reset controller. However, an additional power management IC (PMIC) is required to control the termination voltage. Further, the addition of the PMIC and the reset controller increases the area overhead and power consumption of the IC.
Therefore it would be advantageous to have an IC that can configure an external memory in a self-refresh mode without the need for a memory controller or IO pads, and reduces power consumption of the IC, reduces the transition time required for the IC to go from low power mode to high power mode without increasing the area overhead of the IC.